This invention relates to an integrated circuit, and particularly an integrated circuit with multiple processing cores and which includes a test access port controller (TAP controller) for effecting communication of serial data across the chip boundary.
Test access port controllers are known in the art. TAP controllers are used to effect communication of test data on and off chip via what is known as a JTAG port. The functions of known TAP controllers are defined by IEEE Standard 1149.1-1990. That Standard defines test logic which can be included in an integrated circuit to provide standardised approaches to testing the interconnections between integrated circuits, testing the integrated circuit itself, and observing or modifying circuit activities during the integrated circuit""s xe2x80x9cnormalxe2x80x9d or xe2x80x9cuser modexe2x80x9d operation.
According to the IEEE Standard, the TAP controller is capable of implementing a variety of different test modes. In each of these test modes, test data is supplied to the chip via an input pin of the TAP controller, and resultant data following the test is supplied off-chip via an output pin of the TAP controller. The resultant data is dependent on the test data and is compared with expected data to check the validity of the test. The input and output pins are referred to respectively as TDI and TDO. Many existing integrated circuits already incorporate a TAP controller of this type with the input and output pins TDI and TDO.
Our earlier patent application EP-A-0840217 describes a system which makes use of these pins and the TAP controller to increase the communication facilities of the integrated circuit without multiplexing the pins and thereby violating the standard.
This is particularly useful for diagnostic purposes. That is, where an integrated circuit includes embedded functional circuitry, for example a processor, it is very difficult using existing diagnostic techniques to provide real time non-intrusive monitoring of the functional circuitry. The functional circuitry need not be a processor but could be other functional circuitry, which might include a DMA (Direct Memory Access) engine, or on-chip cache.
In the past, processors (CPUs) were manufactured as a single chip, requiring off-chip access to all their ancillary circuitry, such as memory. As a result, they had a plurality of access pins so that information about the CPU, in particular memory addressing information, was in any event externally available from these access pins.
In addition to memory addressing information, it is useful to be able to obtain status information about the internal state of the processor to ascertain for example such events as interrupts, changes in streams of instructions, setting of flags in various status registers of the CPU, etc.
Nowadays, chips are more complex and contain multiple processing cores. This combined with the increasing complexity of software designed to run on integrated circuit CPUs make debugging and diagnosis more and more difficult.
The technique described in EP-A-0840217 provides a system which greatly simplifies debugging for an integrated circuit with an on-chip processor. However, when more than one independent processing core is integrated on a single chip, it is desirable to debug each core, preferably as independently as possible. Typically, debugging software which runs on a host and which controls the debugging process is different and independent for each target processing core. This is difficult to implement with the system described in EP-A-0840217 because all on and off-chip communications take place via the TAP controller which responds to instructions from a single source only. Thus, although the earlier system does allow for on-chip functionality which comprises more than one processing core, the problem of independence required between the diagnostic facilities for each core and the independence of communication between each diagnostic facility and the corresponding independent software module on the host is not addressed.
According to one aspect of the present invention there is provided an integrated circuit comprising:
a) a serial data input pin and a serial data output pin;
b) on-chip functional circuitry comprising at least two processing cores;
c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins,
wherein the data adaptor comprises:
i) transmit circuitry including means for receiving parallel data and control signals from said on-chip functional circuitry, and
ii) means for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received, and
iii) receive circuitry including means for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits,
iv) means for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and
vi) means for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits.
In the described embodiment the receive circuitry comprises decoding means for decoding an event sequence of said serial bits, said event sequence including said channel identification bits. The event sequence can comprise an event header constituting a data packet. The transmit circuitry can include an event generator which generates an event sequence of bits to identify the communication channel on which data is being transmitted. An event can be generated when the instant communication channel is switched to an alternative communication channel.
Each processing core preferably includes at least one autonomously operating processor. In addition, it can also include on-chip memory and a bus system for communicating with said on-chip memory and also possibly with off-chip memory. In addition, each processing core can include a message converter which formulates messages to be transmitted off-chip via the data adaptor and decodes messages which are received on-chip via the data adaptor.
In order to implement diagnostics, each processing core can comprise a set of registers holding information for diagnostic purposes, said registers being accessible from off-chip via the data adapter and the communication channel associated with that processing core. This allows simultaneous independent debugging of on-chip independent processing cores to be accomplished.
The integrated circuit can comprise a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to on-clip test logic in a first mode of operation and connectable to the data adaptor in a second mode of operation.
The invention also provides a number of different computer systems incorporating an integrated circuit as above defined. In one of those systems, two independently operating off-chip processors are connected to the chip by an off-chip host communications adaptor for independently debugging two on-chip processing cores.
In another system, an off-chip host processor has two independently running debugging applications which can communicate independently via an off-chip adaptor with two on-chip independent processing cores.
In another system, an off-chip host processor executes a debugging application with independently operable interface modules which can communicate independently with on-chip processing cores via an off-chip host adaptor.
The invention also provides a method of effecting communication of messages from one of a plurality of independent processing cores on an integrated circuit to an off-chip host processor, wherein:
a) said one independent processing core formulates a message including a message identifier denoting the nature of the message and a channel identifier denoting the communication channel by which the independent processing core seeks to communicate the message;
b) the message is communicated via the identified communication channel to a data adaptor which adapts the message into a format suitable for communication off-chip;
c) when an alternative independent processing core seeks to communicate a message, a new communication channel is identified for the alternative independent processing core and an event message is generated for transmission off-chip identifying the alternative communication channel.